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? 2009-2016 microchip technology inc. ds20002213b-page 1 24lc16b device selection table features single supply with operation down to 2.5v low-power cmos technology: - active current 1 ma, typical - standby current, 1 a, typical 2-wire serial interface, i 2 c compatible schmitt trigger inputs for noise suppression output slope control to eliminate ground bounce 100 khz and 400 khz clock compatibility page write time 5 ms maximum self-timed erase/write cycle 16-byte page write buffer hardware write-protect esd protection >4,000v more than 1 million erase/write cycles data retention >200 years factory programming available rohs compliant temperature ranges: - extended (m): -55c to +125c description the microchip technology inc. 24lc16b is a 16 kbit electrically erasable prom. the device is organized as eight blocks of 256 x 8-bit memory with a 2-wire serial interface. low-voltage design permits operation down to 2.5v with standby and active currents of only 1 a and 1 ma, respectively. the 24lc16b also has a page write capability for up to 16 bytes of data. the 24lc16b is available in the standard 8-pin soic and 5-lead sot-23 packages. package types block diagram part number v cc range max. clock frequency temp. ranges 24lc16b 2.5v-5.5v 400 khz m soic a0a1 a2 v ss 12 3 4 87 6 5 v cc wp scl sda note: pins a0, a1 and a2 are not used by the 24lc16b (no internal connections). sot-23 sda v ss v cc 1 2 3 5 4 wp scl hv eeprom array page ydec xdec sense amp. memory control logic i/o control logic i/o wp sda scl v cc v ss r/w control latches generator 16k i 2 c serial eeprom extended (-55 c to +125 c) operating temperatures downloaded from: http:///
24lc16b ds20002213b-page 2 ? 2009-2016 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.3v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-55c to +125c esd protection on all pins ???????????????????????????????????????????????????????????????????????????????????????????????????? ???????????????????????????????????????????????????? 4kv table 1-1: dc characteristics ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics extended (m): t a = -55c to +125c, v cc = +2.5v to +5.5v param. no. symbol characteristic min. typ. ( 2 ) max. units conditions d1 v ih high-level input voltage 0.7 v cc v d2 v il low-level input voltage 0.3 v cc v d3 v hys hysteresis of schmitt trigger inputs 0.05 v cc v note 1 d4 v ol low-level output voltage 0.40 v i ol = 3.0 ma, v cc =2.5v d5 i li input leakage current 1 a v in =v ss or v cc d6 i lo output leakage current 1 a v out = v ss or v cc d7 c in pin capacitance (all inputs/outputs) 10 pf v cc = 5.0v ( note 1 ) t a = 25c, f clk =1mhz c out d8 i ccwrite operating current 3 ma v cc = 5.5v, scl = 400 khz d9 i ccread 0 . 0 11m a d10 i ccs standby current 1 a +85c, sda = scl = v cc wp = v ss 5 a +125c, sda = scl = v cc wp = v ss note 1: this parameter is periodically sampled and not 100% tested. 2: typical measurements taken at room temperature. downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 3 24lc16b table 1-2: ac characteristics ac characteristics extended (m): t a = -55c to +125c, v cc = +2.5v to +5.5v param. no. symbol characteristic min. max. units conditions 1f clk clock frequency 400 khz 2 t high clock high time 600 ns 3t low clock low time 1300 ns 4t r sda and scl rise time ( note 1 ) 300 ns note 1 5t f sda and scl fall time 300 ns note 1 6t hd : sta start condition hold time 600 ns 4000 ns 7t su : sta start condition setup time 600 ns 8t hd : dat data input hold time 0 ns note 2 9t su : dat data input setup time 100 ns 10 t su : sto stop condition setup time 600 ns 11 t aa output valid from clock ( note 2 ) 900 ns 12 t buf bus free time: bus time must be free before a new transmission can start 1300 ns 13 t of output fall time from v ih minimum to v il maximum 20+0.1c b 250 ns 14 t sp input filter spike suppression (sda and scl pins) 5 0n s notes 1 and 3 15 t wc write cycle time (byte or page) 5m s 16 endurance 1m cycles page mode, +25c, 5.5v ( note 4 ) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endu rance estimates in a specific application, please consult the total endurance? model which can be obtained from microchips website at www.microchip.com. downloaded from: http:///
24lc16b ds20002213b-page 4 ? 2009-2016 microchip technology inc. figure 1-1: bus timing data figure 1-2: bus timing start/stop 7 5 2 4 8 9 10 12 11 14 6 scl sda in sda out 3 7 6 d3 10 start stop scl sda downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 5 24lc16b 2.0 pin descriptions the descriptions of the pins are listed in tab l e 2 - 1 . table 2-1: pin function table 2.1 serial address/data input/output (sda) sda is a bidirectional pin used to transfer addresses and data into and out of the device. since it is an open-drain terminal, the sda bus requires a pull-up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400 khz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating start and stop conditions. 2.2 serial clock (scl) the scl input is used to synchronize the data transfer to and from the device. 2.3 write-protect (wp) the wp pin must be connected to either v ss or v cc . if tied to v ss , normal memory operation is enabled (read/write the entire memory 000-7ff). if tied to v cc , write operations are inhibited. the entire memory will be write-protected. read operations are not affected. 2.4 a0, a1, a2 the a0, a1 and a2 pins are not used by the 24lc16b. they may be left floating or tied to either v ss or v cc . name 8-pin soic 5-pin sot-23 description a0 1 not connected a1 2 not connected a2 3 not connected v ss 4 2 ground sda 5 3 serial address/data i/o scl 6 1 serial clock wp 7 5 write-protect input v cc 8 4 +2.5v to +5.5v power supply downloaded from: http:///
24lc16b ds20002213b-page 6 ? 2009-2016 microchip technology inc. 3.0 functional description the 24lc16b supports a bidirectional, 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, while a device receiving data is defined as a receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions, while the 24lc16b works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 4.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined ( figure 4-1 ). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must end with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is determined by the master device and is, theoretically, unlimited (although only the last sixteen will be stored when doing a write operation). when an overwrite does occur it will replace data in a first-in first-out (fifo) fashion. 4.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable-low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24lc16b) will leave the data line high to enable the master to generate the stop condition. figure 4-1: data transfer sequence on the serial bus note: the 24lc16b does not generate any acknowledge bits if an internal programming cycle is in progress. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 7 24lc16b 5.0 device addressing a control byte is the first byte received following the start condition from the master device ( figure 5-1 ). the control byte consists of a four-bit control code. for the 24lc16b, this is set as 1010 binary for read and write operations. the next three bits of the control byte are the block select bits (b2, b1, b0). they are used by the master device to select which of the eight 256 word-blocks of memory are to be accessed. these bits are, in effect, the three most significant bits (msb) of the word address. it should be noted that the protocol limits the size of the memory to eight blocks of 256 words, therefore, the protocol can support only one 24lc16b per system. the last bit of the control byte defines the operation to be performed. when set to 1 , a read operation is selected. when set to 0 , a write operation is selected. following the start condition, the 24lc16b monitors the sda bus, checking the device type identifier being transmitted and, upon receiving a 1010 code, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24lc16b will select a read or write operation. figure 5-1: control byte allocation figure 5-2: address sequence bit assignments operation control code block select r/w read 1010 block address 1 write 1010 block address 0 10 10 b2 b1 b0 r/w ack start bit read/write bit s slave address acknowledge bit control code block select bits 1010 b 2 b 1 b 0 r/w a 7 a 0 control byte address low byte control code block select bits downloaded from: http:///
24lc16b ds20002213b-page 8 ? 2009-2016 microchip technology inc. 6.0 write operation 6.1 byte write following the start condition from the master, the device code (four bits), the block address (three bits) and the r/w bit, which is a logic low, are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow once it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24lc16b. after receiving another acknowledge signal from the 24lc16b, the master device will transmit the data word to be written into the addressed memory location. the 24lc16b acknowledges again and the master generates a stop condition. this initiates the internal write cycle and, during this time, the 24lc16b will not generate acknowledge signals ( figure 6-1 ). 6.2 page write the write control byte, word address and the first data byte are transmitted to the 24lc16b in the same way as in a byte write. however, instead of generating a stop condition, the master transmits up to 16 data bytes to the 24lc16b, which are temporarily stored in the on-chip page buffer and will be written into memory once the master has transmitted a stop condition. upon receipt of each word, the four lower-order address pointer bits are internally incremented by one. the higher-order 7 bits of the word address remain constant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an internal write cycle will begin ( figure 6-2 ). 6.3 write protection the wp pin allows the user to write-protect the entire array (000-7ff) when the pin is tied to v cc . if tied to v ss , the write protection is disabled. note: when doing a write of less than 16 bytes, the data in the rest of the page is refreshed along with the data bytes being written. this will force the entire page to endure a write cycle; for this reason, endurance is specified per page. note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page-size) and end at addresses that are integer multiples of [page size C 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 9 24lc16b figure 6-1: byte write figure 6-2: page write s p bus activity master sda line bus activity st a r t st o p control byte word address data ac k ac k ac k 10 1 0 b2 b1 b0 0 block select bits s p bus activity master sda line bus activity st a r t control byte word address ( n) data (n) data (n + 15) st o p ac k ac k ac k ac k ac k data (n + 1) b1 b2 b0 1 0 1 0 0 block select bits downloaded from: http:///
24lc16b ds20002213b-page 10 ? 2009-2016 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally-timed write cycle and ack polling can then be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, no ack will be returned. if the cycle is complete, the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for a flow diagram of this operation. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 11 24lc16b 8.0 read operation read operations are initiated in the same way as write operations, with the exception that the r/w bit of the slave address is set to 1 . there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 24lc16b contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to 1 , the 24lc16b issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24lc16b discontinues transmission ( figure 8-1 ). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is accomplished by sending the word address to the 24lc16b as part of a write operation. once the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the inter- nal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a 1 . the 24lc16b will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24lc16b will discontinue transmission ( figure 8-2 ). 8.3 sequential read sequential reads are initiated in the same way as a random read, except that once the 24lc16b transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24lc16b to transmit the next sequentially addressed 8-bit word ( figure 8-3 ). to provide sequential reads, the 24lc16b contains an internal address pointer that is incremented by one upon completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 8.4 noise protection the 24lc16b employs a v cc threshold detector circuit which disables the internal erase/write logic if the vcc is below 1.5v at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. downloaded from: http:///
24lc16b ds20002213b-page 12 ? 2009-2016 microchip technology inc. figure 8-1: current address read figure 8-2: random read figure 8-3: sequential read sp bus activity master sda line bus activity st o p control byte data (n) ac k no a c k st a r t 1 0 1 0 1 b2 b1 b0 block select bits s p s bus activity master sda line bus activity st a r t st o p control byte ac k word address (n) control byte st a r t data (n) ac k ac k n o a c k 10 10 0 b2b1 b0 11 0 0 1 b2 b1b0 block select bits block select bits p bus activity master sda line bus activity st o p control byte ac k n o a c k data (n) data (n + 1) data (n + 2) data (n + x ) ac k ac k ac k 1 downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 13 24lc16b 9.0 packaging information 9.1 package marking information 8-lead soic (3.90 mm) example: 24lc16bm sn 1606 13f 3 e 5-lead sot-23 example: aadn6 061l7 part number 1st line marking codes soic sot-23 24lc16b 24lc16bt aadny xxxxxxxt xxxxyyww nnn legend: xx...x part number or part number code t temperature (m) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code (2 characters for small packages) jedec ? designator for matte tin (sn) note : for very small packages with no room for the jedec ? designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e * standard otp marking consists of microchip part number, year code, week code, and traceabili ty code. downloaded from: http:///
24lc16b ds20002213b-page 14 ? 2009-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 15 24lc16b note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24lc16b ds20002213b-page 16 ? 2009-2016 microchip technology inc. downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 17 24lc16b n b e e1 d 1 2 3 e e1 a a1 a2 c l l1 downloaded from: http:///
24lc16b ds20002213b-page 18 ? 2009-2016 microchip technology inc. noe: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 19 24lc16b appendix a: revision history revision a (10/2009) initial release of this document. revision b (03/2016) added 5-lead sot-23 package. downloaded from: http:///
24lc16b ds20002213b-page 20 ? 2009-2016 microchip technology inc. notes: downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 21 24lc16b the microchip website microchip provides online support via our website at www.microchip.com . this website is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the website contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip website at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the website at: http://microchip.com/supportl downloaded from: http:///
24lc16b ds20002213b-page 22 ? 2009-2016 microchip technology inc. notes: downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 23 24lc16b product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device: 24lc16b: = 2.5v, 16 kbit i 2 c serial eeprom tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: m = C55c to +125c package: sn = plastic soic (3.90 mm body), 8-lead ot = plastic sot-23, 5-lead (tape and reel only) examples: a) 24lc16b-m/sn = extended temp., 2.5v, soic package. b) 24lc16bt-m/ot = tape and reel, extended temp., 2.5v, sot-23 package. note 1: tape and reel identifier only appears in the catalog part number description. this identi- fier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. [x] (1) tape and reel option downloaded from: http:///
24lc16b ds20002213b-page 24 ? 2009-2016 microchip technology inc. notes: downloaded from: http:///
? 2009-2016 microchip technology inc. ds20002213b-page 25 24lc16b information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2009-2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0339-5 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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